External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 12-53
The external master is given two cycles to start its access after a posed CLKOUT in which bus grant was
given to it by the internal arbiter (BG asserted, BB negated for 2 cycles). This means when BG is negated
(to take away bus grant from the external master), the EBI does not start an access of its own for three
cycles (one extra cycle in order to detect external BB assertion). If the external master jumps on the bus
(by asserting BB
) during the two-cycle window, the EBI detects the BB assertion and delays starting its
access until the external master access has completed (BB
negated for two cycles). Figure 12-34 shows
this 2-cycle window of opportunity.
I
Figure 12-34. Internal Arbitration, Two-Cycle Window-of-Opportunity
Figure 12-35 shows example timing for the case of one master using internal arbitration (master 0), while
another master is configured for external arbitration (master 1). In this case, the BR signals of each master
are connected together, since only master 1 drives BR. The BG signals of each master are also connected
together, since only master 0 drives BG. See Figure 12-38 for an example of these connections.
Figure 12-35. Internal/External Arbitration Timing Diagram (EARP = 1)
Latest cycle M1 can assert BB
Using internal arbiter for Master 0,
external arbitration for Master 1
M1 receives bus grant and BB
is negated for second cycle
Earliest cycle M1 can assert BB
CLKOUT
BR
BG
BB (Case 1)
BB
(Case 2)
Window-of-
opportunity
*
Earliest cycle M0 can assert BB
if M1 has not asserted BB yet.
*
M0 receives BB negated for
for the second cycle
Fastest request –
>
grant possible
M1 receives BG and BB negated for the second cycle
Using internal arbiter for Master 0, external arbitration for Master 1
CLKOUT
BR
BB
ADDR + ATTR
1
CS[n]
BG
TA
TS
Both
masters
off
Master 1
negates BB
and
‘turns off’
(three-states controls)
Master 0
asserts BB and
‘turns on’
(drives controls)
Master 1
asserts BB and
‘turns on’
(drives controls)
1
ATTR refers to control signals such as RD_WR
and TSIZ.
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