External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 12-55
MCU owner busy 1 0 or 1 0 X 0 X 1 X External bus wait
MCU owner busy 1 0 or 1 0 X X 1 0 X External owner
MCU owner busy 1 0 or 1 0 X 0 X 0 X External owner
MCU owner busy 1 0 or 1 1 X 0 X 0 X MCU owner idle
External bus wait 0 0 or 1
13
X
14
XX X 1 X
8
External bus wait
External bus wait 0 0 or 1 X X X X 0 X External owner
1
The Output column for BB shows the value EBI drives on BB for each state.
2
The Input column for BR shows the value driven on BR the previous cycle from an external source. The state machine uses
the previous clock value to avoid potential speed paths with trying to calculate bus grant based on a late-arriving external BR
signal.
3
The Input column for BB shows the value driven on BB the previous cycle from an external source. The state machine uses
the previous clock value to ensure adequate switching time between masters driving the same signal and to avoid potential
speed paths.
4
This represents an internal EBI signal that indicates whether an internal request for use of the external bus is pending. Once
a transaction for a pending request has been started on the external bus, this internal signal is cleared. The state machine
uses the previous clock value to avoid potential speed paths with trying to calculate bus grant based on a late-arriving internal
request signal.
5
This represents an internal EBI signal that indicates whether the internal MCU (0) or external master (1) currently has higher
priority.
6
This represents an internal EBI signal that indicates whether an EBI-mastered transaction on the bus is in progress this cycle
or is going to start the next cycle (and thus has already been committed internally).
7
This represents an internal EBI signal that indicates whether the bus was granted to an external master (BG =0, previous
BB = 1) during the previous 3 cycles.
8
RGB is always low in this state, thus it is ignored in the transition logic.
9
RGB is always low in this state, thus it is ignored in the transition logic.
10
The ETP signal is never asserted in states where it is shown as an ‘X’ for all transitions.
11
RGB is always high in this state, thus it is ignored in the transition logic.
12
IRP is ignored (treated as 1) in the MCU_WAIT state because the EBI does not optimally support an internal master cancelling
its bus request. If IRP is negated in this state, the EBI still grants the internal master the bus as if IRP was still asserted, and
a few cycles be wasted before the external master be able to grab the bus again (depending on BR
, BB, etc., according to
normal transition logic).
13
The default BB output is 0 for this state. However, anytime the EBI transitions from a state where BB = 0 to a state where
BB
= hiZ, there is one external cycle (in this state) where the EBI drives BB = 1 to actively negate the pin before letting go to
hiZ. In the case where a second granted internal request (IRP = 1, ETP=1) is ready to start just before the transition to the hiZ
state is about to occur (during the BB
= 1active negate cycle), then BB is driven back to 0 to start the next access without ever
leaving this state or going to hiZ.
14
BR is ignored (treated as 0) in the EXT_WAIT state because the EBI does not optimally support an external master cancelling
its bus request. If BR is negated in this state, the EBI still grants the external master the bus as if BR was still asserted, and a
few cycles be wasted while the external master ‘window-of-opportunity’ is satisfied before the internal master be able to grab
the bus again (depending on BR
, BB, etc., according to normal transition logic).
Table 12-23. Truth Table for Internal Arbiter (continued)
State
Outputs Previous Inputs External Status
Next State
BG BB
1
BR
2
BB
3
MCU
internal
request
pending
(IRP)
4
External
has
higher
priority
(EHP)
5
MCU
external
transaction
in progress
(or starting
next cycle)
(ETP)
6
Recent
BG
(RBG)
7
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