NXP Semiconductors MPC5566 - Page 737

Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5566 Microcontroller Reference Manual, Rev. 2
17-58 Freescale Semiconductor
Figure 17-40 illustrates the counter cycle for several A1 values. Register A1 is loaded with the A2 value
at the cycle boundary. Thus any value written to A2 within cycle (n) is updated to A1 at the next cycle
boundary, and therefore is used on cycle (n+1). The cycle boundary between cycle (n) and cycle (n+1) is
defined as the first clock cycle of cycle (n+1). Flags are set when A1 matches occur.
Figure 17-40. eMIOS MCB Mode Example — Up Operation
Figure 17-41 illustrates the MCB up/down counter mode. The A1 register is updated at the cycle boundary.
If A2 is written in cycle (n), this new value is used in cycle (n+1) for the next A1 match.
Flags are generated only at an A1 match if MODE[5] is 0. If MODE[5] is 1, flags are also generated at the
cycle boundary.
Figure 17-41. eMIOS MCB Mode Example — Up/Down Operation
EMIOS_CCNTRn
Time
Write to A2
Match A1
Match A1 Match A1
Write to A2
0x000001
0x000005
0x000006
0x000007
FLAG set event
0x000005 0x000007
A2 value
A1 value
0x000006
0x000005
0x000007
0x000007
Note: A2 value transferred to A1 according to OUn bit.
EMIOS_CCNTRn
Time
Write to A2
Match A1
Match A1
Write to A2
0x000001
0x000005
0x000006
0x000007
FLAG set event
0x000005 0x000007
A2 value
A1 value
0x000006
0x000005
0x000007
Note: A2 value transferred to A1 according to OUn bit.