NXP Semiconductors MPC5566 - Page 738

Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 17-59
Figure 17-42 provides a more detailed illustration of the A1 update process in up counter mode. The A1
load signal is generated based on the detection of the internal counter reaching one, and has the duration
of one system clock cycle. During the load pulse A1 still holds its previous value. It is actually updated at
the second system clock cycle.
Figure 17-42. eMIOS MCB Mode Example — Up Operation A1 Register Update
Figure 17-43 illustrates the A1 register update process in up/down counter mode. A2 can be written at any
time within cycle (n) to be used in cycle (n+1). Thus, A1 receives the new value at the next cycle boundary.
The EMIOS_OUDR[n] bits can be used to disable the update of A1 register.
Figure 17-43. eMIOS MCB Mode Example — Up/Down Operation A1 Register Update
A1 value 0x000008
0x000008
0x000001
EMIOS_CCNTR
0x000004
0x000006
A2 value 0x000008 0x000004 0x000006
0x000002
0x000004 0x000006
Write to A2
A1 load signal
1
8
4
6
Selected Counter = 1
Time
Cycle n
Cycle n+1
Cycle n+2
Match A1 Match A1Match A1
Write to A2
Note: A2 value transferred to A1 according to OUn bit.
EMIOS_CCNTR
Time
Write to A2
Match A1 Match A1
Write to A2
0x000001
0x000005
0x000006
0x000005
A2 value
A1 value
0x000006
0x000005
Selected Counter = 1
A1 load signal
0x000006 0x000006
0x000006
Cycle n Cycle n+1 Cycle n+2
Note: A2 value transferred to A1 according to OUn bit (the transfer is triggered by the A1 load signal).