Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5566 Microcontroller Reference Manual, Rev. 2
17-64 Freescale Semiconductor
Figure 17-47 shows the operation of the output disable feature in OPWFMB mode. Unlike OPWFM mode,
the output disable forces the channel output flip-flop to the EDPOL bit value. This functionality targets
applications that use active high signals and a high to low transition at A1 match. For such cases, clear
EDPOL to 0.
Figure 17-47. eMIOS OPWFMB Mode Example — Active Output Disable
The output disable has a synchronous operation, meaning that the assertion of the output disable input
signal causes the channel output flip-flop to transition to EDPOL at the next system clock cycle. If the
output disable input is negated, the output flip-flop transitions at the following A1 or B1 match.
In Figure 17-47 it is assumed that the output disable input is enabled and selected for the channel (refer to
Section 17.3.1.7, “eMIOS Channel Control Register (EMIOS_CCRn),” for a detailed description of the
ODIS and ODISSL bits and selection of the output disable inputs).
The FORCMA and FORCMB bits allow the software to force the output flip-flop to the level
corresponding to a match on comparators A or B respectively. Similar to a B1 match, FORCMB clears the
internal counter. The FLAG bit is not set when the FORCMA or FORCMB bits are set.
Cycle n Cycle n+1 Cycle n+2
A1 value
B1 value
B2 value
0x000008
0x000002
0x000006
0x000008
0x000001
EMIOS_CCNTRn
0x000004
0x000006
MODE[0] = 1
A2 value
0x000002 0x000004 0x000006
0x000002
0x000004
0x000006
0x000008 0x000006
Output flip-flop
Write to B2
Match A1 Match B1
Match B1
A1/B1 load signal
Due to B1 match
FLAG set event
cycle n-1
Time
Write to A2
Match A1
Write to A2 Match B1
EDPOL = 0
To Next Page
Loading...
