NXP Semiconductors MPC5566 - Page 745

Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5566 Microcontroller Reference Manual, Rev. 2
17-66 Freescale Semiconductor
dead time insertion, the output PWM duty cycle is equal to the difference between register A1 and register
B1, and for a trailing edge dead time insertion, the output PWM duty cycle is equal to the sum of register
A1 and register B1. The MODE[6] bit selects between trailing and leading dead time insertion,
respectively.
NOTE
Synchronize the internal prescaler of the OPWMCB channel with the MCB
channel prescaler and set them to the same value. This allows the A1 and B1
registers to represent the same time scale for duty cycle and dead time
insertion.
Figure 17-49 illustrates loading of the A1 and B1 registers, which occurs when the selected counter bus
reaches the value one. This counter value defines the cycle boundary. Values written to A2 or B2 within
cycle (n) are loaded into A1 or B1 registers and are used to generate matches in cycle (n+1).
Figure 17-49. eMIOS OPWMCB Mode Example — A1/B1 Register Loading
The EMIOS_OUDR[n] bit can be used to disable the A1 and B1 updates, thus allowing the loading of these
registers to be synchronized with the load of A1 or B1 registers in others channels. By using the update
disable bit, the A1 and B1 registers can be updated in the same counter cycle.
In this mode A1 matches set the internal counter to one. When operating with leading edge dead time
insertion, the first A1 match resets the internal counter to 0x000001. When a match occurs between
register B1 and the internal time base, the output flip-flop is set to the value of the EDPOL bit. In the
following match between A1 and the selected time base, the output flip-flop is set to the complement of
the EDPOL bit. This sequence repeats continuously.
Selected
Time
Write to A2
Match A1
Match A1
Write to A2
0x000001
0x000005
0x000006
0x000015
A1 value
A2 value
0x000020
0x000015
Selected counter = 1
A1/B1 load signal
0x000020 0x000016
0x000016
Cycle n Cycle n+1 Cycle n+2
B1 value
0x000004
B2 value
0x000004 0x000006
0x000005
0x000005 0x000006
counter bus