NXP Semiconductors MPC5566 - Page 751

Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5566 Microcontroller Reference Manual, Rev. 2
17-72 Freescale Semiconductor
Figure 17-53 illustrates operation in OPWMB mode with A1/B1 matches and the transition of the channel
output flip-flop. In this example EDPOL is zero.
Figure 17-53. eMIOS OPWMB Mode Example — Matches and Flags
The output flip-flop transitions are based on the negative edges of the A1 and B1 match signals.
Figure 17-53 shows the value of A1 being set to zero in cycle (n+1). In this case the match positive edge
is used instead of the negative edge to transition the output flip-flop.
1
4
A1 match negative
6
A1 value 0x000004
A1 match
Output flip-flop
Selected
Time
B1 match negative
B1 match
B1 value 0x000006
System clock
Prescaled clock
A2 value 0x000000
0x000000
A1 match positive edge detect
1
8
6
FLAG bit set
EDPOL = 0
A1 match negative
B1 match negative
A1 match positive
edge detection
edge detection
edge detection
edge detect
Cycle n
Cycle n+1
Write to A2
edge detect
counter bus