NXP Semiconductors MPC5566 - Page 752

Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 17-73
Figure 17-54 illustrates the channel operation for 0% duty cycle. The A1 match signal positive edge occurs
at the same time as the B1 = 8 signal negative edge. In this case the A1 match has precedence over the B1
match, causing the output flip-flop to remain at the EDPOL value, thus generating a 0% duty cycle.
Figure 17-54. eMIOS OPWMB Mode Example — 0% Duty Cycle
1
4
A1 match negative
A1 value 0x000004
A1 match
Output flip-flop
Selected
Time
B1 match negative
B1 match
B1 value 0x000006
System clock
Prescaled clock
A2 value 0x000000
0x000000
A1 match positive edge detect
1
8
FLAG bit set
EDPOL = 0
A1 match negative
B1 match negative
A1 match positive
edge detection
edge detection
edge detection
edge detect
Cycle n
Cycle n+1
Write to A2
edge detect
8
counter bus