Rohde & Schwarz RTE - I²C (Option R&S RTE-K1); The I²C Protocol

Protocol analysis
R&S
®
RTE
522User Manual 1326.1032.02 ─ 20
Where applicable, frequently used values are provided in a "Predefined values" list
below the pattern table, for example, reserved end words of data packets in the UART
protocol.
13.2 I²C (option R&S RTE-K1)
The Inter-Integrated Circuit is a simple, low-bandwidth, low-speed protocol used for
communication between on-board devices.
● The I²C protocol.................................................................................................... 522
● I²C configuration....................................................................................................524
● I²C trigger.............................................................................................................. 526
●
I
2
C label list........................................................................................................... 531
● I²C decode results.................................................................................................533
● Search on decoded I²C data................................................................................. 535
13.2.1 The I²C protocol
This chapter provides an overview of protocol characteristics, data format, address
types and trigger possibilities. For detailed information, read the "I2C-bus specification
and user manual" available on the NXP manuals webpage at http://www.nxp.com/.
I²C characteristics
Main characteristics of I²C are:
●
Two-wire design: serial clock (SCL) and serial data (SDA) lines
●
Master-slave communication: the master generates the clock and addresses the
slaves. Slaves receive the address and the clock. Both master and slaves can
transmit and receive data.
●
Addressing scheme: each slave device is addressable by a unique address. Multi-
ple slave devices can be linked together and can be addressed by the same mas-
ter.
●
Read/write bit: specifies if the master reads (=1) or writes (=0) the data.
●
Acknowledge: takes place after every byte. The receiver of the address or data
sends the acknowledge bit to the transmitter.
The R&S RTE supports all operating speed modes: high-speed, fast mode plus, fast
mode, and standard mode.
Data transfer
The format of a simple I²C message (frame) with 7-bit addressing consists of the fol-
lowing parts:
●
Start condition: a falling slope on SDA while SCL is high
●
7-bit address of the slave device that either is written to or read from
●
R/W bit: specifies if the data is written to or read from the slave
I²C (option R&S
RTE-K1)