Mixed signal option (MSO, R&S RTE-B1)
R&S
®
RTE
916User Manual 1326.1032.02 ─ 20
Figure 14-5: State trigger settings for trigger source = parallel bus
Clock source
Selects the digital channel of the clock signal.
Remote command:
TRIGger<m>:PARallel:DATatoclock:CSOurce[:VALue] on page 1913
TRIGger<m>:PARallel:STATe:CSOurce:VALue on page 1913
TRIGger<m>:PARallel:SPATtern:CSOurce[:VALue] on page 1913
Clock edge
Sets the edge of the clock signal. The crossing of the clock edge and the logical
threshold defines the time at which the logical states and the bus value are analyzed.
Remote command:
TRIGger<m>:PARallel:STATe:CSOurce:EDGE on page 1917
Channel states
Available for "Trigger Source"= "Par. Bus1/2/3/4"
For each digital channel that is used in the bus, set the required state: 1, 0, or X (don't
care).
Remote command:
TRIGger<m>:PARallel:STATe:BIT<0..15> on page 1917
Logical expression
Defines a logic combination of several digital channels as trigger condition if "Logic" is
set for "Source". The "Qualification Editor" supports the entry of the expression.
Remote command:
TRIGger<m>:PARallel:TIMeout:EXPRession[:DEFine] on page 1913
TRIGger<m>:PARallel:STATe:EXPRession[:DEFine] on page 1913
TRIGger<m>:PARallel:PATTern:EXPRession[:DEFine] on page 1913
TRIGger<m>:PARallel:SPATtern:EXPRession[:DEFine] on page 1913
14.3.1.7 Pattern
The pattern trigger identifies a logical state of several logically combined digital chan-
nels (pattern) and a time limitation (holdoff). The pattern definition is defined by the log-
Trigger
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