Infineon Technologies TC1796 - Page 1035

Infineon Technologies TC1796

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TC1796

System Units (Vol. 1 of 2)

Register Overview

User’s Manual 18-46 V2.0, 2007-07

Regs, V2.0

GPTA1_

PLLREV

GPTA1 Phase Locked

Loop Reload Register

F000 20D0

H

U, SV U, SV 0000 0000

H

GPTA1_

PLLDTR

GPTA1 Phase Locked

Loop Delta Register

F000 20D4

H

U, SV U, SV 0000 0000

H

GPTA1_

CKBCTR

GPTA1 Clock Bus Control

Register

F000 20D8

H

U, SV U, SV 0000 FFFF

H

– Reserved F000 20DC

H

nBE nBE –

GPTA1_

GTCTR0

GPTA1 Global Timer

Control Register 0

F000 20E0

H

U, SV U, SV 0000 0000

H

GPTA1_

GTREV0

GPTA1 Global Timer

Reload Value Register 0

F000 20E4

H

U, SV U, SV 0000 0000

H

GPTA1_

GTTIM0

GPTA1 Global Timer

Register 0

F000 20E8

H

U, SV U, SV 0000 0000

H

– Reserved F000 20EC

H

nBE nBE –

GPTA1_

GTCTR1

GPTA1 Global Timer

Control Register 1

F000 20F0

H

U, SV U, SV 0000 0000

H

GPTA1_

GTREV1

GPTA1 Global Timer

Reload Value Register 1

F000 20F4

H

U, SV U, SV 0000 0000

H

GPTA1_

GTTIM1

GPTA1 Global Timer

Register 1

F000 20F8

H

U, SV U, SV 0000 0000

H

– Reserved F000 20FC

H

nBE nBE –

GPTA1_

GTCCTRn

GPTA1 Global Timer Cell

Control Register n

(n = 00-31)

F000 2100

H

+ n × 08

H

+ 00

H

U, SV U, SV 0000 0000

H

GPTA1_

GTCXRn

GPTA1 Global Timer Cell

X Register n

(n = 00-31)

F000 2100

H

+ n

×

08

H

+ 04

H

U, SV U, SV 0000 0000

H

GPTA1_

LTCCTRn

GPTA1 Local Timer Cell

Control Register n

(n = 00-63)

F000 2200

H

+ n × 08

H

+ 00

H

U, SV U, SV 0000 0000

H

GPTA1_

LTCXRn

GPTA1 Local Timer Cell

X Register n

(n = 00-63)

F000 2200

H

+ n × 08

H

+ 04

H

U, SV U, SV 0000 0000

H

Table 18-21 Address Map of GPTA1 (cont’d)

Short Name Description Address Access Mode Reset Value

Read Write

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