TC1796
System Units (Vol. 1 of 2)
LMB External Bus Unit
User’s Manual 13-63 V2.0, 2007-07
EBU, V2.0
13.8.6.3 Interfacing to Motorola-style Devices
Figure 13-23 gives an example of accessing a Motorola-style demultiplexed device for
read and write accesses. The chip select signal CSx is used to generate the AS input for
the Motorola-style device. The MR/W signal maintains its level (according on whether
the cycle is read or write) from the Address Phase to the Recovery Phase during each
access.
Externally controlled wait states (see Page 13-57) are used to synchronize with the
DTACK output from the device. A Motorola-style device asserts DTACK during a read
access to signal that the data is available on the data bus. During a write access, the
falling edge of DTACK indicates that the Motorola-style device has completed the write
access and the data can be removed from the data bus. This can be accomplished by
use of the WAIT signal with inverse polarity (selected by EBU_BUSCONx.WAITINV = 1)
with the following limitations:
1. During read accesses, a minimum command phase of three LMBCLK cycles must be
used to ensure correct recognition of the WAIT input.
2. Only the falling edge of DTACK is recognized by the WAIT pin, and the user must
insert sufficient recovery cycles to ensure that the DTACK pin has returned high
before the next external bus cycle starts (i.e. before the next falling edge of any CSx
signal). Typically, Motorola-style devices de-assert DTACK after the rising edge of
their AS input (which is connected to a EBU CSx output).
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