TC1796
Peripheral Units (Vol. 2 of 2)
Controller Area Network (MultiCAN) Controller
User’s Manual 22-202 V2.0, 2007-07
MultiCAN, V2.0
22.9.3.1 Clock Control Registers
The clock control register makes it possible to control (enable/disable) the module
control clock f
CLC
.
Note: Additional details on the clock control register functionality are described in section
“Clock Control Register CLC” on Page 3-24 of the TC1796 User’s Manual
System Units part (Volume 1).
CAN_CLC
CAN Clock Control Register (000
H
) Reset Value: 0000 0003
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
r
1514131211109876543210
0
FS
OE
SB
WE
E
DIS
SP
EN
DIS
S
DIS
R
r rwwrwrw r rw
Field Bits Type Description
DISR 0rwModule Disable Request Bit
Used for enable/disable control of the module.
DISS 1rModule Disable Status Bit
Bit indicates the current status of the module.
SPEN 2rwModule Suspend Enable for OCDS
Used to enable the Suspend Mode.
EDIS
3rw
External Request Disable
Used to control external clock disable request.
SBWE 4wModule Suspend Bit Write Enable for OCDS
Determines whether SPEN and FSOE are write-
protected.
FSOE 5rwFast Switch Off Enable
Used for fast clock switch off in Suspend Mode.
0 [31:6] r Reserved
Read as 0; should be written with 0.
To Next Page
Loading...
Need help?
General