Infineon Technologies TC1796 User Manual

TC1796
Peripheral Units (Vol. 2 of 2)
Synchronous Serial Interface (SSC)
User’s Manual 20-46 V2.0, 2007-07
SSC, V2.1
20.3 SSC0/SSC1 Module Implementation
This section describes SSC0/SSC1 module interfaces with the clock control, port
connections, interrupt control, and address decoding.
20.3.1 Interfaces of the SSC Modules
Figure 20-16 shows the TC1796-specific implementation details and interconnections of
the SSC0/SSC1 modules.
Figure 20-16 SSC0/SSC1 Module Implementation and Interconnections
MCA05791
Clock
Control
Address
Decoder
Interrupt
Control
f
SSC0
Address
Decoder
Interrupt
Control
To
DMA
f
CLC0
f
SSC1
f
CLC1
Clock
Control
SSC0_RDR
SSC0_TDR
To
DMA
SSC1_RDR
SSC1_TDR
Port 2
Control
. . .
MRSTB
MTSR
Master
SLSI1
SLSO[7:2]
MRSTA
MTSRB
MRST
MTSRA
SCLKB
SCLK
SCLKA
Slave
Slave
Master
Slave
Master
Port 6
Control
MRSTB
MTSR
Master
SLSO[7:2]
MRSTA
MTSRB
MRST
MTSRA
SCLKB
SCLK
SCLKA
Slave
Slave
Master
Master
MTSR0
MRST0
SCLK0
P6.5 /
MRST1
P6.4 /
MTSR1
P6.6 /
SCLK1
SLSI0
P2.2 /
SLSO2
P2.7 /
SLSO7
P6.7 /
SLSI1
SLSI[7:2]
1)
SLSI1
Slave
SLSI[7:2]
1)
SSC Enabled
M/S Selected
SLSO0
SLSO1
1) These lines are not connected
SLSO1
SLSO0
SSC0
Module
(Kernel)
8-Stage RXFIFO
8-Stage TXFIFO
SSC1
Module
(Kernel)
EIR
TIR
RIR
EIR
TIR
RIR
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2

Infineon Technologies TC1796 Specifications

General

Brand	Infineon Technologies
Model	TC1796
Category	Controller
Language	English