TC1796
System Units (Vol. 1 of 2)
General Purpose I/O Ports and Peripheral I/O Lines
User’s Manual 10-78 V2.0, 2007-07
Ports, V2.0
10.12.3 Port 9 Register
The following registers are available on Port 8:
Note: The complete address map of Port 9 is described in Table 18-18 on Page 18-31
of this TC1796 System Units (Vol. 1 of 2) User’s Manual.
10.12.3.1 Port 9 Output Register
The basic P9_OUT register functionality is described on Page 10-13. Port lines P9.[15:9]
are not available. Therefore, the P9_OUT bits P[15:9] should be written with 0 and are
always read as 0.
10.12.3.2 Port 9 Output Modification Register
The basic P9_OMR register functionality is described on Page 10-14. Port lines
P9.[15:9] are not available. Therefore, the P9_OMR bits PS[15:9] and PR[15:9] are not
implemented. These bits should always be written with 0.
Table 10-26 Port 9 Registers
Register
Short Name
Register Long Name Offset
Address
Description
see
P9_OUT Port 9 Output Register 0000
H
below
1)
1) These registers are listed and noted here in the Port 9 section because they differ from the general port
register description given in Section 10.2.
P9_OMR Port 9 Output Modification Register 0004
H
P9_IOCR0 Port 9 Input/Output Control Register 0 0010
H
Page 10-7
P9_IOCR4 Port 9 Input/Output Control Register 4 0014
H
Page 10-8
P9_IOCR8 Port 9 Input/Output Control Register 8 0018
H
Page 10-79
1)
P9_IN Port 9 Input Register 0024
H
Page 10-79
1)
P9_PDR Port 9 Pad Driver Mode Register 0040
H
Page 10-80
1)
P9_ESR Port 9 Emergency Stop Register 0050
H
Page 10-80
1)
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