TC1796
Peripheral Units (Vol. 2 of 2)
Controller Area Network (MultiCAN) Controller
User’s Manual 22-142 V2.0, 2007-07
MultiCAN, V2.0
22.6.3 Setup of the Scheduler Entries
The entries in the scheduler memory can be set up only when all bits NCRx.CCE of the
TTCAN nodes sharing the scheduler memory are set at the same time. Write actions to
the scheduler memory while not all corresponding bits NCRx.CCE = 1 are not taken into
account. The scheduler entries can always be read out for verification purposes.
22.6.4 Reading the Scheduler Entries
After a time mark has been reached, the scheduler instructions for the following time
window are read by the scheduler. This “collected” information can be read out from the
scheduler timing status and from the scheduler instruction status register. The
information becomes valid when the next time mark is reached. The information
collected between time mark n-1 and time mark n becomes valid when the time mark n
is reached.
Figure 22-32 Collecting the Instructions
22.6.4.1 Instructions During a Basic Cycle
The handling of entries collected between the time marks n-1 and n is defined as follows:
• Time Mark Entry:
The time mark value is defining the compare value for the time mark n.
• Interrupt Entry:
Valid interrupt information (INP+ 4 enable bits) can generate an interrupt when the
time mark n is reached, depending on the flags RECF and TRAF (they are
MCT05858
Instructions for Window n-1 Instructions for Window n-1
Time Window n-1 Time Window n
Frame Reception Frame Transmisstion
Transmit Enable Window
Time Mark
n-1
Time Mark
n
Time Mark
n+1
Collect
Instructions
Collect
Instructions
Arbitration Arbitration
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