TC1796
Peripheral Units (Vol. 2 of 2)
General Purpose Timer Array (GPTA)
User’s Manual 24-191 V2.0, 2007-07
GPTA, V2.0
24.3.10 I/O Sharing Unit Registers
The three registers MRACTL, MRADIN, and MRADOUT are used to write data to and
read data from the GPTA Multiplexer Register Array FIFO. The Multiplexer Register
Array FIFO controls the operation of the Input/Output Line Sharing Unit (see
Section 24.2.4.5).
The Multiplexer Register Array Control register controls the operation of the Multiplexer
Register Array FIFO.
MRACTL
Multiplexer Register Array Control Register
(038
H
) Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
r
1514131211109876543210
0FIFOFILLCNT 0
FIFO
FUL
L
WCR
ES
MA
EN
rr rrwrw
Field Bits Type Description
MAEN 0rwMultiplexer Array Enable
Bit field MAEN enables/disables the programming and
the interconnections of the multiplexer array.
0
B
Multiplexer array is disabled; all cell inputs are
driven with 0, GPTA I/O lines (pins) are
disconnected and FIFO writing is enabled.
1
B
Multiplexer array is enabled; all cell and I/O line
interconnections are established as previously
programmed and FIFO writing is disabled.
WCRES 1wWrite Count Reset
Writing WCRES with 1 while the array is disabled
(MAEN = 0), resets the write cycle counter to zero and
the FIFO written sequentially (initialized). WCRES is
always read as 0.
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