TC1796
Peripheral Units (Vol. 2 of 2)
Micro Second Channel (MSC)
User’s Manual 21-78 V2.0, 2007-07
MSC, V2.0
21.3.6 Interrupt Control Registers
In the TC1796, the two service request outputs SR[1:0] of each MSC module are
connected to one interrupt node. The upper two service request outputs SR[3:2] of each
MSC module are not connected to interrupt nodes, but can be used as DMA requests
(see Table 21-13).
Note: Additional details on service request nodes and the service request control
registers are described on Page 14-3 of the TC1796 User’s Manual System Units
part (Volume 1).
SRC1
Service Request Control Register 1 (F8
H
) Reset Value: 0000 0000
H
SRC0
Service Request Control Register 0 (FC
H
) Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
r
1514131211109876543210
SET
R
CLR
R
SRR SRE 0 TOS 0 SRPN
w w rh rw r rw r rw
Field Bits Type Description
SRPN [7:0] rw Service Request Priority Number
TOS 10 rw Type of Service Control
SRE 12 rw Service Request Enable
SRR 13 rh Service Request Flag
CLRR 14 w Request Clear Bit
SETR 15 w Request Set Bit
0 [9:8], 11,
[31:16]
r Reserved
Read as 0; should be written with 0.
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