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Infineon Technologies TC1796 - 8 Data Memory Unit

Infineon Technologies TC1796
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TC1796
System Units (Vol. 1 of 2)
Data Memory Unit
User’s Manual 8-1 V2.0, 2007-07
DMU, V2.0
8 Data Memory Unit
The Data Memory Unit (DMU) shown in Figure 8-1 contains a total of 80 Kbyte of fast
static RAM memory:
64 Kbyte SRAM memory that can be used as
Normal data storage
Overlay memory
Data Flash mirror memory
16 Kbyte of standby memory (SBRAM)
SRAM and SBRAM are parity protected
With overlay address generation and control logic, that makes it possible to redirect
data accesses to the PMU-based memories into the DMU or emulation memory.
Figure 8-1 Block Diagram of the Data Memory Unit (DMU)
Note: DMU memories cannot be accessed by the PCP using burst transfers (BCOPY
instruction).
DMU
MCB05648
DMU
Control
Overlay Address
Generation &
Control
SRAM
64 KB
SBRAM
16 KB
To/From Data
Local Memory Bus
DLMB Interface
Slave Master
To
Program
Local
Memory
Bus
SRAM = Data Memory
DFSRAM = Data Flash shadow RAM
OVRAM = RAM with overlay capability
SBRAM = Stand-by RAM
V
DD
SlaveMaster
64
64
64
64
PLMB (LMI) Interface
V
DDRAM
V
DDSBRAM
Parity
Control/Check
To SCU
(DMU Memory Parity Error)

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