TC1796
System Units (Vol. 1 of 2)
LMB External Bus Unit
User’s Manual 13-61 V2.0, 2007-07
EBU, V2.0
13.8.6.2 Interfacing to INTEL-style Devices
Figure 13-22 shows an example of accessing an INTEL-style demultiplexed device for
read and write accesses. It shows the insertion of delay cycles (shown shaded) to adjust
the access cycle to the device’s timing requirements.
Both read and write accesses start with a two.cycle Address Phase followed by a two-
cycle Command Delay Phase.
For the read access, the Command Delay Phase is followed by a three-cycle Command
Phase. At the end of the Command Phase, the data is read (latched) by the EBU. A one-
cycle Recovery Phase is inserted at the end of the cycle. At the start of this Recovery
Phase, all control signals return to their non-active levels.
For the write access, the Command Delay Phase is followed by a two cycle Command
Phase. During a write access, it is possible to insert a Data Hold Phase to satisfy the data
hold time requirements of the device. In the example the Data Hold Phase consists of
two cycles (DH1 and DH2). During the Data Hold Phase, the RD/WR control signal is
driven to the non-active state, but the data and address are still driven on the bus.
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