Infineon Technologies TC1796 - 3.3.2 Clock Control Register CLC

TC1796
System Units (Vol. 1 of 2)
Clock System and Control
User’s Manual 3-24 V2.0, 2007-07
Clock, V2.0
3.3.2 Clock Control Register CLC
All CLC registers have basically the same bit and bit field layout. However, not all CLC
register functions are implemented for each peripheral unit. Table 3-9 defines in detail
which bits and bit fields of the CLC registers are implemented for each clock control
register.
The CLC register controls the generation of the peripheral module clock which is derived
from the system clock. The following functions for the module are associated with the
CLC register:
• Peripheral clock static on/off control
• Module clock behavior in Sleep Mode
• Operation during Debug Suspend Mode
• Fast Shut-off Mode control
MOD_CLC
Clock Control Register (00
H
) Reset Value: Module-specific
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
r
1514131211109876543210
RMC 0
FS
OE
SB
WE
E
DIS
SP
EN
DIS
S
DIS
R
rw r rwwrwrwrhrw
Field Bits Type Description
DISR 0rwModule Disable Request Bit
Used for enable/disable control of the module.
0
B
Module disable is not requested
1
B
Module disable is requested
DISS 1rhModule Disable Status Bit
Bit indicates the current status of the module
0
B
Module is enabled
1
B
Module is disabled
If the RMC field is implemented and if it is 0, DISS is set
to 1 automatically.