Infineon Technologies TC1796 - 2.4.1.1 Implementation-specific Core Special Function Registers

TC1796
System Units (Vol. 1 of 2)
CPU Subsystem
User’s Manual 2-11 V2.0, 2007-07
CPU, V2.0
2.4.1.1 Implementation-specific Core Special Function Registers
This section describes the implementation-specific Program Status Word (PSW) which
is an extension of the PSW description in the TriCore 1 Architecture Manual.
The PSW status flags used for FPU operations overlay the status flags used for
Arithmetic Logic Unit (ALU) operations of the CPU. The non-shaded areas in the PSW
register description define the implementation-specific bits/bit fields.
The Interrupt Control Register is also an implementation-specific CSFR. Its Arbitration
Cycle Control implementation-specific details are described on Page 14-8.
PSW
Program Status Word (F7E1FE04
H
) Reset Value: 0000 0B80
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
C
or
FS
V
or
FI
SV
or
FV
AV
or
FZ
SAV
or
FU
FX RM
0
rwh rwh rwh rwh rwh rwh rw r
1514131211109876543210
0 PRS IO IS GW CDE CDC
r rwh rwh rwh rwh rwh rwh
Field Bits Type Description
RM [25:24] rw FPU Rounding Mode Selection
FX 26 rwh FPU Inexact Flag
SAV 27 rh Sticky Advance Overflow Flag
FU rwh FPU Underflow Flag
AV 28 rwh Advance Overflow Flag
FZ FPU Divide by Zero Flag
SV 29 rwh Sticky Overflow Flag
FV FPU Overflow Flag
V 30 rwh Overflow Flag
FI FPU Invalid Operation Flag
C 31 rwh Carry Flag
FS FPU Some Exception Flag