TC1796
System Units (Vol. 1 of 2)
Data Memory Unit
User’s Manual 8-3 V2.0, 2007-07
DMU, V2.0
8.4 Parity Protection for DMU Memories
In the TC1796, the SBRAM and SRAM memory blocks of the DMU are equipped with a
parity error detection logic that makes it possible to detect parity errors. In case of a parity
error a NMI is generated.
Note that before using parity protection for SBRAM and SRAM the first time after a
power-on reset operation (before setting the corresponding parity error enable bits), the
corresponding memories must be completely initialized by a user program that writes
every memory location of it once.
More details about the parity control for on-chip memories are described in Section 5.5
on Page 5-37.
8.5 Data Access Overlay Functionality
The DMU overlay functionality provides the capability to redirect data read accesses
from internal or external code memory to data accesses from the DMU SRAM. This
functionality makes it possible, for example, to modify program parameters (which are
typically stored in the code memory) during run time of a program. Instruction fetches are
not affected by the PMU data read access redirection capability. Note that read and write
data accesses from/to code memory are redirected.
The basic overlay scheme is shown in Figure 8-2.
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