TC1796
System Units (Vol. 1 of 2)
Program Memory Unit
User’s Manual 7-36 V2.0, 2007-07
PMU, V2.0
7.2.9 Flash Interrupt Generation and Control
One interrupt request can be issued by the Flash module. The related interrupt control
register is located in the DMA controller.
The Flash interrupt can be issued when any of the following events occur:
• End-of-busy: programming or erase operation of Flash bank finished
• Command sequence error
• Protection error
• Single-bit error in PFLASH
• Single-bit error in DFLASH
• Double-bit error in PFLASH
• Double-bit error in DFLASH
The source of the Flash interrupt is indicated in the Flash Status Register FSR by the
corresponding busy and error flags. Every interrupt source is disabled after reset, and
can be enabled individually via dedicated enable bits in the Flash Configuration Register
FCON.
The end-of-busy interrupt becomes active whenever a programming or erasing
operation is finished. At this event, one of the three FSR busy flags PBUSY, D0BUSY,
or D1BUSY is cleared from 1 to 0. End-of-busy interrupts are enabled by setting the
FCON.EOBM bit.
The error flags in the Flash Status Register are controlled independently of the interrupt
configuration as defined in the FCON register. Thus, they may be polled without interrupt
support. When set, an error flag has to be cleared by the user with the Clear Status
command. All error flags are also cleared with any reset.
Errors, which are caused by a reset during program or erase operation, are not indicate,
but its detection is supported via the PROG and ERASE flags in the Flash Status
Register FSR. These two flags are cleared only with a power-on reset. Therefore, it is
possible to detect an aborted Flash operation, if after every terminated Flash operation
these flags are immediately cleared by the user with the Clear Status command, and if
these flags are checked with every user-boot after reset (all except power-on reset).
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