TC1796
Peripheral Units (Vol. 2 of 2)
Synchronous Serial Interface (SSC)
User’s Manual 20-47 V2.0, 2007-07
SSC, V2.1
Each of the SSC modules is supplied by a separate clock control, interrupt control, and
address decoding logic. Two interrupt outputs can be used to generate DMA requests.
The SSC0 I/O lines are connected to dedicated pins. The SSC1 I/O lines are connected
to Port 2 and Port 6. The SLSOx outputs of SSC0 and SSC1 are wired as alternate
function to six I/O lines of Port 2. Two SLSOx outputs of SSC0 are connected to
dedicated pins. Note that only SSC0 contains an 8-stage Receive and Transmit FIFO.
SSC1 does not provide any FIFO functionality.
20.3.2 SSC0/SSC1 Module Related External Registers
Figure 20-17 summarizes the module-related external registers which are required for
SSC0/SSC1 programming (see also Figure 20-15 for the module kernel-specific
registers).
Figure 20-17 SSC0/SSC1 Implementation-Specific Special Function Registers
MCA05792
SSC0_CLC
SSC1_CLC
SSC0_TSRCP2_IOCR0
SSC0_RSRC
SSC0_ESRC
SSC1_TSRC
SSC1_RSRC
SSC1_ESRC
Clock Control
Registers
Interrupt
Registers
Port Registers
P2_IOCR4
SSC0_FDR
SSC1_FDR
P6_IOCR4
P2_PDR
P6_PDR
To Next Page
Loading...