TC1796
System Units (Vol. 1 of 2)
CPU Subsystem
User’s Manual 2-34 V2.0, 2007-07
CPU, V2.0
2.6.4 DMI Registers
Two control registers and two trap flag registers are implemented in the DMI. These
registers and their bits are described in this section.
Figure 2-14 DMI Registers
Access to DMI control registers must only be made with double-word aligned word
accesses. An access not conforming to this rule, or an access that does not follow the
specified privilege mode (Supervisor mode, Endinit-protection), or a write access to a
read-only register, will lead to a bus error if the access was from the LMB Bus, or to a
trap, flagged in DMI_STR/DMI_ATR register in case of a CPU load/store access.
Table 2-9 DMI Registers
Register
Short Name
Register Long Name Address Description
DMI_ID DMI Module Identification Register F87F FC08
H
Page 2-35
DMI_CON DMI Control Register F87F FC10
H
Page 2-36
DMI_STR DMI Synchronous Trap Flag Register F87F FC18
H
Page 2-38
DMI_ATR DMI Asynchronous Trap Flag Register F87F FC20
H
Page 2-39
DMI_CON1 DMI Control Register 1 F87F FC28
H
Page 2-37
DMI_CON
MCA05598_mod
DMI_CON1
DMI_STR
Control Registers Trap Flag Registers
DMI_ATR
Module Identification
Register
DMI_ID
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