TC1796
Peripheral Units (Vol. 2 of 2)
Micro Link Interface (MLI)
User’s Manual 23-141 V2.0, 2007-07
MLI, V2.0
23.5.6 Access Protection
23.5.6.1 Fixed Address Range Definition
Table 23-15 below shows the fixed address ranges covered by the access protection
(for read and write) of the MLI modules. The access enable bits AER.AENx are related
to address range x. If bit AENx is set, read/write accesses to the corresponding address
range x are allowed. Some of the access enable bits AENx control more than one
address range.
Table 23-15 MLI Access Protection Address Ranges
Access Protection Range Related Module(s)
No. x Enable Bit
in AER
Selected Address Range
0 AEN0 F000 0000
H
to F000 00FF
H
F010 C200
H
to F010 C2FF
H
SCU, incl. WDT
MEMCHK
1 AEN1 F000 0100
H
to F000 01FF
H
F010 0000
H
to F010 00FF
H
SBCU
RBCU
2 AEN2 F000 0200
H
to F000 02FF
H
STM
3 AEN3 F000 0400
H
to F000 04FF
H
OCDS
4 AEN4 F000 0800
H
to F000 08FF
H
F000 0900
H
to F000 09FF
H
MSC0
MSC1
5 AEN5 F000 0A00
H
to F000 0AFF
H
ASC0
6 AEN6 F000 0B00
H
to F000 0BFF
H
ASC1
7 AEN7 F000 0C00
H
to F000 0FFF
H
P0, P1, P2, P3
8 AEN8 F000 1000
H
to F000 17FF
H
P4, P5, P6, P7, P8, P9, P10
9 AEN9 F000 1800
H
to F000 2FFF
H
GPTA0, GPTA1, LTCA2
10 AEN10 F000 3C00
H
to F000 3EFF
H
DMA
11 AEN11 F000 4000
H
to F000 5FFF
H
MultiCAN
12 AEN12 F004 0000
H
to F005 FFFF
H
PCP Registers,
PCP Data Memory
13 AEN13 F006 0000
H
to F006 7FFF
H
PCP Code Memory
14 AEN14 F010 0100
H
to F010 01FF
H
SSC0
15 AEN15 F010 0200
H
to F010 02FF
H
SSC1
16 AEN16 F010 0300
H
to F010 03FF
H
FADC
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