TC1796
System Units (Vol. 1 of 2)
Direct Memory Access Controller
User’s Manual 12-15 V2.0, 2007-07
DMA, V2.0
Combined Software/Hardware-controlled Mode
Figure 12-9 shows how software- and hardware-controlled modes can be combined. In
the example, the first DMA transfer is triggered by software when setting
STREQ.SCHmn. Hardware requests are still disabled. After hardware requests have
been enabled by setting HTREQ.ECHmn, subsequent DMA transfers are triggered now
by hardware request coming from the CHmn_REQ line.
In the example, DMA channel mn operates in Single Mode (CHCRmn.CHMODE = 0). In
this mode, TRSR.HTREmn becomes cleared by hardware when CHSRmn.TCOUNT
reaches 0 at the end of the DMA transaction.
Figure 12-9 Transaction Start by Software, Continuation by Hardware
12.1.4.4 Error Conditions
The source move error flag ERRSR.FPI0SER indicates an FPI Bus error on bus 0 (SPB)
that occurred during a source move (read) of a DMA transaction. The destination move
error flag ERRSR.FPI0DER indicates an FPI Bus error on bus 0 (SPB) that occurred
during a destination move (write) of a DMA transaction.
The transaction lost error flag ERRSR.TRLmn indicates if a DMA request for a DMA
channel mn has been lost.
In the case of a read error, the write action is not executed, but the destination address
is updated.
MCT05688
tc = initial transfer count
TR0 TRn-1 TRnTR1
tc-1tc002
1
TRSR.CHmn
Writing
STREQ.SCHmn=1
Writing
HTREQ.ECHmn=1
TRSR.HTREmn
CHmn_REQ
DMA Transfer mn
CHSRmn.
TCOUNT
INT
(triggered at the end
of a transaction with
IRDV = 0)
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