TC1796
System Units (Vol. 1 of 2)
On-Chip System Buses and Bus Bridges
User’s Manual 6-42 V2.0, 2007-07
Buses, V2.0
6.5.5.3 OCDS Registers
SBCU_DBCNTL
SBCU Debug Control Register (30
H
) Reset Value: 0000 7003
H
RBCU_DBCNTL
RBCU Debug Control Register (30
H
) Reset Value: 0000 7003
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ON
BOS
3
ON
BOS
2
ON
BOS
1
ON
BOS
0
0ONA20ONA1 0 ONG
rw rw rw rw r rw r rw r rw
1514131211109876543210
0
CON
COM
2
CON
COM
1
CON
COM
0
0RA0OAEO
r rwrwrw r w r r r
Field Bits Type Description
EO 0rStatus of BCU Debug Support Enable
This bit is controlled by the Cerberus and enables the
BCU debug support.
0
B
BCU debug support is disabled.
1
B
BCU debug support is enabled.
(default after reset)
OA 1rStatus of BCU Breakpoint Logic
0
B
The BCU breakpoint logic is disarmed. Any
further breakpoint activation is discarded.
1
B
The BCU breakpoint logic is armed.
The OA bit is set by writing a 1 to bit RA. When OA is
set, registers xBCU_DBGNTT, xBCU_DBADRT, and
xBCU_DBBOST are reset.
RA 4wRearm BCU Breakpoint Logic
Writing a 1 to this bit rearms BCU breakpoint logic and
sets bit OA = 1. RA is always reads as 0.
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