TC1796
System Units (Vol. 1 of 2)
Watchdog Timer
User’s Manual 16-2 V2.0, 2007-07
WDT, V2.0
16.2 Features of the Watchdog Timer
The major features of the WDT are summarized here. The WDT is implemented in the
System Control Unit (SCU) module of the TC1796. Figure 16-1 gives an overview of its
interface signals.
• 16-bit Watchdog counter
• Selectable input frequency: f
SYS
/256 or f
SYS
/16384
• 16-bit user-definable reload value for normal Watchdog operation, fixed reload value
for Time-Out and Prewarning Modes
• Incorporation of the ENDINIT bit and monitoring of its modifications
• Sophisticated Password Access mechanism with fixed and user-definable password
fields
• Proper access always requires two write accesses. The time between the two
accesses is monitored by the WDT and limited.
• Access Error Detection: Invalid password (during first access) or invalid guard bits
(during second access) trigger the Watchdog reset generation.
• Overflow Error Detection: An overflow of the counter triggers the Watchdog reset
generation.
• Watchdog function can be disabled; access protection and ENDINIT monitor function
remain enabled.
• Double Reset Detection: If a Watchdog induced reset occurs twice, a severe system
malfunction is assumed and the TC1796 is held in reset until a power-on or hardware
reset occurs. This prevents the device from being periodically reset if, for instance,
connection to the external memory has been lost such that even system initialization
could not be performed.
• Important debugging support is provided through the reset prewarning operation by
first issuing an NMI to the CPU before finally resetting the device after a certain
period of time.
Figure 16-1 Interface of the WDT Inside and Outside the SCU Module
MCA05750
SCU Module
To CPU
NMI
To System
ENDINIT
To System
Reset
Watchdog Timer (WDT)
Address
Decoder
WDTTIM[15] WDT_RSTWDT_NMI
f
SYS
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