TC1796
System Units (Vol. 1 of 2)
Watchdog Timer
User’s Manual 16-16 V2.0, 2007-07
WDT, V2.0
16.4.6.4 Prewarning Mode Details
Prewarning Mode is always entered immediately after a Watchdog error condition was
detected. This can be either an access error to register WDT_CON0 or an overflow of
the counter in Normal or Time-Out Mode. This mode indicates that a reset of the device
is imminent. Operation of the WDT in this mode can not be altered or stopped, except
through a reset.
Note: In Prewarning Mode, the device does not have to wait for the end of the Time-out
Period and the reset. After having saved required state in the NMI routine,
Table 16-7 WDT Prewarning Mode
State /
Action
Description
Entry Detection of a Watchdog error:
• Overflow of timer WDTTIM.
• Access error to register WDT_CON0 (either on a password or Modify
Access) in Time-Out, Normal, or Disable modes.
Actions on
Entry
• NMIWDT in register NMISR is set (this triggers an NMI request to the
CPU).
• WDTTIM is set to FFFC
H
.
• WDTPR is set to 1; WDTDS is set to 0; WDTIS retains its value.
• WDTTO retains its previous value: If entry into Prewarning Mode was
from Time-Out Mode, WDTTO is 1. In all other cases, WDTTO is 0.
• Bits WDTAE and WDTOE indicate whether Prewarning Mode was
entered due to an access or an overflow error. They have been set
accordingly on exit of the previous mode.
Operation • Timer WDT_TIM starts counting up from FFFC
H
with frequency
selected through WDTIS.
• Register WDT_CON0 can be accessed in this mode as usual.
However, the WDT will not change its mode anymore, regardless
whether valid or invalid accesses are made to WDT_CON0. For invalid
accesses to WDT_CON0 (Password or Modify Access), however, bit
WDTAE in WDT_SR will be set.
• Register WDT_CON1 can not be written to in Prewarning Mode, even
if bit ENDINIT = 0. Write access to WDT_CON1 is totally prohibited.
Exit • Prewarning Mode can not be disabled, prolonged, or terminated
(except through a reset). The timer will increment until it overflows from
FFFF
H
to 0000
H
, which then causes a system reset. Bit WDTRST in
register RSTSR is set in this case.
Next Mode Reset
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