TC1796
Peripheral Units (Vol. 2 of 2)
Fast Analog-to-Digital Converter (FADC)
User’s Manual 26-12 V2.0, 2007-07
FADC, V2.0
In case of a f
CLC
/ f
CTx
ratio between 1 and 2, a mixture of both divide factor definitions
occurs depending on the divider ratio as programmed by the fractional divider value.
Therefore, it is recommended that this ratio should not be used.
26.1.5 Control Logic
26.1.5.1 Conversion Control
A conversion is started when at least one of the CRSR.CRFx bits is set. A running
conversion cannot be aborted and is indicated by the busy flag CRSR.BSYx set. The
corresponding bit CRSR.CRFx is cleared by hardware when the conversion starts.
26.1.5.2 Static Channel Priority
If more than one conversion request flag CRSR.CRFx (x = 0-3) is set, the channels are
converted according to a priority scheme as defined by the bit field GCR.CRPRIO
(without respecting the status of the current filter sequences).
26.1.5.3 Dynamic Priority Assignment
If dynamic priority assignment is enabled (GCR.DPAEN = 1), a channel that has the only
active gate signal (signal ECHTIMx in Figure 26-4) among the four channels gets the
highest priority (GCR.CRPRIO is set to the number of the channel). If more than one
channel gating signal is active, GCR.CRPRIO is not changed automatically. In this case,
it can be changed by software.
f
CLC
/ f
CTx
= 1 Channel x timer divide factor = CTREL + 2
1 < f
CLC
/ f
CTx
< 2 Not recommended to be used!
2 ≤ f
CLC
/ f
CTx
Channel x timer divide factor = CTREL + 1
Table 26-4 Static Channel Request Priority
Priority GCR.CRPRIO
00
B
01
B
10
B
11
B
High
Low
Channel 0 Channel 1 Channel 2 Channel 3
Channel 1 Channel 2 Channel 3 Channel 0
Channel 2 Channel 3 Channel 0 Channel 1
Channel 3 Channel 0 Channel 1 Channel 2
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