TC1796
System Units (Vol. 1 of 2)
General Purpose I/O Ports and Peripheral I/O Lines
User’s Manual 10-24 V2.0, 2007-07
Ports, V2.0
10.3.3.2 Port 0 Software Configuration Selection
The logic levels of the sixteen Port 0 lines are latched into the register SCU_SCLIR (SCU
Software Configuration Latched Inputs Register) when the hardware reset goes inactive
(at the rising edge of HDRST). This feature makes it possible to use Port 0 lines for
software configuration selection purposes.
Depending on the TC1796 device used, several of the SWOPT bits (meaning several of
the P0 lines) are reserved and may not be used by a user program for software
configuration selection purposes. Detail see Section 10.3.3.3 on the next page.
Note: The reset value (bits “X”) of the register SCU_SCLIR is defined by the circuitry
connected to Port 0 at the rising edge of HDRST. Port 0 lines are set to inputs with
pull-up devices connected (reset values of port input/output control registers).
SCU_SCLIR
SCU Software Configuration Latched Inputs Register
(F0000038
H
) Reset Value: 0000 XXXX
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
r
1514131211109876543210
SWO
PT15
SWO
PT14
SWO
PT13
SWO
PT12
SWO
PT11
SWO
PT10
SWO
PT9
SWO
PT8
SWO
PT7
SWO
PT6
SWO
PT5
SWO
PT4
SWO
PT3
SWO
PT2
SWO
PT1
SWO
PT0
rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh rh
Field Bits Type Function
SWOPTx
(x = 0-15)
xrhSoftware Configuration Bits
These bits show the state of pin P0.x that was latched
with the last rising edge of HDRST.
0
B
P0.x state/logic level latched by HDRST is 0.
1
B
P0.x state/logic level latched by HDRST is 1.
0 [31:16] r Reserved
Read as 0.
To Next Page
Loading...
Need help?
General