TC1796
Peripheral Units (Vol. 2 of 2)
General Purpose Timer Array (GPTA)
User’s Manual 24-28 V2.0, 2007-07
GPTA, V2.0
24.2.2.4 Digital Phase Locked Loop Cell (PLL)
The GPTA provides a digital Phase Locked Loop cell (PLL) with a frequency multiplier
function. An input signal edge is used as a trigger to generate a programmable number
of GPTA module clocks f
GPTA
on the output signal line. The four signal output lines of the
DCM units can be used as PLL trigger input. The PLL control unit distributes the desired
number of GPTA clocks in regular time intervals over the input signal period length. The
PLL can automatically follow an acceleration or deceleration of the input signal.
Alternatively, an external software routine may handle the input signal’s period length
variation.
The PLL includes a 4-channel input multiplexer, a 16-bit timer, a 16-bit step register, a
24-bit reload register, a 24-bit adder, a 24-bit multiplexer, a 25-bit delta register extended
by one sign bit and a PLL control unit (see Figure 24-18).
The following registers are assigned to the Phase Locked Loop cell:
• PLLCTR = Phase Locked Loop Control Register (see Page 24-165)
• PLLMTI = Phase Locked Loop Microtick Register (see Page 24-166)
• PLLCNT = Phase Locked Loop Counter Register (see Page 24-167)
• PLLSTP = Phase Locked Loop Step Register (see Page 24-167)
• PLLREV = Phase Locked Loop Reload Register (see Page 24-168)
• PLLDTR = Phase Locked Loop Delta Register (see Page 24-168)
• SRSC0 = Service Request State Clear Register 0 (see Page 24-206)
• SRSS0 = Service Request State Set Register 0 (see Page 24-208)
Three output signals are available on the PLL cell:
• PLL signal output line
• Uncompensated PLL signal output line
• Service request line
To Next Page
Loading...
Need help?
General