Infineon Technologies TC1796 - 26.1.2 Conversion Timing

TC1796
Peripheral Units (Vol. 2 of 2)
Fast Analog-to-Digital Converter (FADC)
User’s Manual 26-8 V2.0, 2007-07
FADC, V2.0
The conversion result for FADC channel x is given by the following equation:
(26.1)
The absolute value of the result V
Mx
is limited to V
FAREF
. The mapping of the conversion
result
V
Mx
to the binary result RCHx.ADRES is as follows (see also Table 26-1):
For single-ended measurements, the following values are taken into account:
•if ENP
x
= 0 then V
FAINxP
= V
FAREFM
•if ENN
x
= 0 then V
FAINxN
= V
FAREFM
26.1.2 Conversion Timing
The conversion time of the FADC is determined by the frequency of clock f
FADC
. The
conversion time defined below includes sampling, converting, and storing of the
conversion result.
(26.2)
Clock f
FADC
is generated outside the FADC kernel in a product specific clock control unit
(see Page 26-58).
V
Mx
= -V
FAREF
leads to RCHx.ADRES = 00 0000 0000
B
V
Mx
= 0 leads to RCHx.ADRES = 10 0000 0000
B
V
Mx
= +V
FAREF
leads to RCHx.ADRES = 11 1111 1111
B
Conversion Result V
Mx
GAIN
x
V
FAINxP
V
FAREFM
–()V
FAREFM
V
FAINxN
–()+()=
with V
FAREFM
V
FAGND
V
FAREF
V
FAGND
–()2⁄+=
Conversion Time
FADC
21
1
f
FADC
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