EasyManuals Logo

Infineon Technologies TC1796 User Manual

Infineon Technologies TC1796
2150 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #323 background imageLoading...
Page #323 background image
TC1796
System Units (Vol. 1 of 2)
On-Chip System Buses and Bus Bridges
User’s Manual 6-30 V2.0, 2007-07
Buses, V2.0
Figure 6-11 Grant Trigger Generation
6.5.4.4 Combination of Triggers
The combination of the four debug trigger signals to the single BCU breakpoint trigger
event is defined via the bits CONCOM[2:0] of register xBCU_DBCNTL (see
Figure 6-12). The two address trigger signals are combined to one address trigger that
is further combined with signal status and grant trigger signals. A logical AND or OR
combination can be selected for the BCU breakpoint trigger generation.
Figure 6-12 BCU Breakpoint Trigger Combination Logic
MCA05638
Grant
Trigger
SBCU_DBGRNT
DMA
H
LFI
DMA
L
CBL
Cerberus is granted as
bus master, low priority
&
&
DMA is granted as bus
master, low priority
&
&
&
PCP CBH
LFI Bridge is granted as
bus master
DMA is granted as bus
master, high priority
PCP is granted as bus
master
Cerberus is granted as
bus master, high priority
&
SBCU_DBCNTL
ONG
&
1
MCA05639_mod
Address 1 Trigger
Signal Status Trigger
xBCU_DBCNTL
x = “S“ for SBCU
x = “R“ for RBCU
CONCOM2 CONCOM1 CONCOM0
AND/OR
Selection
Address 2 Trigger
Grant Trigger
AND/OR
Selection
AND/OR
Selection
BCU
Breakpoint
Trigger
Address
Trigger

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the Infineon Technologies TC1796 and is the answer not in the manual?

Infineon Technologies TC1796 Specifications

General IconGeneral
BrandInfineon Technologies
ModelTC1796
CategoryController
LanguageEnglish