TC1796
Peripheral Units (Vol. 2 of 2)
Micro Second Channel (MSC)
User’s Manual 21-32 V2.0, 2007-07
MSC, V2.0
21.1.5.1 Data Frame Interrupt
A data frame interrupt can be generated when either the first or the last data bit of the
downstream channel is shifted out and becomes available at the SO output line (see also
Figure 21-6). Bit ICR.EDIEI selects which case is selected.
Figure 21-23 Data Frame Interrupt Control
21.1.5.2 Command Frame Interrupt
A command frame interrupt can be generated at the end of a downstream channel
command frame (see also Figure 21-5).
Figure 21-24 Command Frame Interrupt Control
MCA05817_mod
DEDI
ISR
Data Frame
Interrupt
(to Int. Comp.)
EDI
Set
Software
Clear
ISC
SDEDI
CDEDI
EDIE = 00, 11
≥1
Software
Set
Hardware
Set
EDIE
ICR
01
10
2
First data bit shifted
Last data bit shifted
MCA05818_mod
ECIE
ICR
Command
Frame Interrupt
(to Int. Comp.)
ECI
DECI
ISR
Software
Clear
Set
End of a command
frame detected
ISC
SDECI
CDECI
Software
Set
Hardware
Set
≥1
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