TC1796
System Units (Vol. 1 of 2)
Interrupt System
User’s Manual 14-25 V2.0, 2007-07
Interrupt, V2.0
14.10 Non-Maskable Interrupt
Although called an interrupt, the Non-Maskable Interrupt (NMI) is actually serviced as a
trap, since it is not interruptible and does not follow the standards for regular interrupts.
In the TC1796, four different events can generate an NMI trap:
• A transition on the NMI input pin
• An error or wake-up signal from the Watchdog Timer
• The PLL becomes unlocked
• The occurrence of an SRAM parity error in an on-chip memory block
The type of NMI trap is indicated in the NMI Status Register (NMISR).
14.10.1 External NMI Input
An external NMI event is generated when a one-to-zero transition is detected at the
external NMI input pin. NMISR.NMIEXT is set in this case. The NMI pin is sampled at the
system clock frequency. A transition is recognized when one sample shows a 1 and the
next sample shows a 0. Subsequent 0-samples or a 0-to-1 transition do not trigger any
action.
NMI is equipped with a noise suppression filter which suppresses glitches below 10 ns
pulse width. NMI pulses with a width above 100 ns are safely recognized as a valid
signal. The noise suppression filter is switched-off when pin BYPASS = 1.
14.10.2 Phase-Locked Loop NMI
The PLL clock generation unit sets the NMIPLL flag when it detects a loss in the
synchronization with the external oscillator clock input. This condition means that the
PLL clock frequency is no longer stable, and that the PLL will now decrease to its VCO
clock base frequency.
14.10.3 Watchdog Timer NMI
The Watchdog Timer sets the NMIWDT flag for two conditions:
• A Watchdog Timer error has occurred
• Bit 15 of the Watchdog Timer is set while the CPU is in idle mode
A Watchdog Timer error can produce an NMI event because:
• Access to register WDT_CON0 was attempted improperly, or
• The Watchdog Timer overflowed either in Time-Out Mode or in Normal Watchdog
Timer Mode.
When the CPU is in Idle Mode and the Watchdog Timer is not disabled, an increment of
the Watchdog Timer counter from 7FFF
H
to 8000
H
(that is, when bit 15 of the timer is set
to 1) sets the NMIWDT bit to wake up the CPU.
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