TC1796
System Units (Vol. 1 of 2)
General Purpose I/O Ports and Peripheral I/O Lines
User’s Manual 10-73 V2.0, 2007-07
Ports, V2.0
10.11.3 Port 8 Register
The following registers are available on Port 8:
Note: The complete address map of Port 8 is described in Table 18-17 on Page 18-30
of this TC1796 System Units (Vol. 1 of 2) User’s Manual.
10.11.3.1 Port 8 Output Register
The basic P8_OUT register functionality is described on Page 10-13. Port lines P8.[15:8]
are not available. Therefore, the P8_OUT bits P[15:8] should be written with 0 and are
always read as 0.
10.11.3.2 Port 8 Output Modification Register
The basic P8_OMR register functionality is described on Page 10-14. Port lines
P8.[15:8] are not available. Therefore, the P8_OMR bits PS[15:8] and PR[15:8] are not
implemented. These bits should always be written with 0.
10.11.3.3 Port 8 Input Register
The basic P8_IN register functionality is described on Page 10-17. Port lines P8.[15:8]
are not available. Therefore, the P8_IN bits P[15:8] are always read as 0.
10.11.3.4 Port 8 Emergency Stop Register
The basic P8_ESR register functionality is described on Page 10-16. At Port 8, only port
lines P8.[7:0] are implemented. Therefore, the P8_ESR bits EN[15:8] are not
implemented. They are always read as 0 and should be written with 0.
Table 10-24 Port 8 Registers
Register
Short Name
Register Long Name Offset
Address
Description
see
P8_OUT Port 8 Output Register 0000
H
below
1)
1) These registers are listed here in the Port 8 section because they differ from the general port register
description given in Section 10.2.
P8_OMR Port 8 Output Modification Register 0004
H
P8_IOCR0 Port 8 Input/Output Control Register 0 0010
H
Page 10-7
P8_IOCR4 Port 8 Input/Output Control Register 4 0014
H
Page 10-8
P8_IN Port 8 Input Register 0024
H
below
1)
P8_PDR Port 8 Pad Driver Mode Register 0040
H
Page 10-74
1)
P8_ESR Port 8 Emergency Stop Register 0050
H
below
1)
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