TC1796
Peripheral Units (Vol. 2 of 2)
Synchronous Serial Interface (SSC)
User’s Manual 20-6 V2.0, 2007-07
SSC, V2.1
selects the leading edge or the trailing edge for each function. Bit CON.PO selects the
level of the clock line in the idle state. For an idle-high clock, the leading edge is a falling
one, a 1-to-0 transition (see Figure 20-3).
Figure 20-3 Serial Clock SCLK Phase and Polarity Options
20.1.2.2 Full-Duplex Operation
The description in this section assumes that the SSC is used with software controlled bi-
directional GPIO port lines that have open-drain capability (see also Section 20.1.2.5).
The various devices are connected through three lines. The definition of these lines is
always determined by the master. The line connected to the master’s data output pin
MTSR is the transmit line, the receive line is connected to its data input line MRST, and
the clock line is connected to pin SCLK. Only the device selected for master operation
generates and outputs the serial clock on pin SCLK. All slaves receive this clock, so their
pin SCLK must be switched to input mode. The output of the master’s shift register is
connected to the external transmit line, which in turn is connected to the slaves’ shift
register input. The output of the slaves’ shift register is connected to the external receive
line in order to enable the master to receive the data shifted out of the slave. The external
connections are hard-wired, with the function and direction of these pins determined by
the master or slave operation of the individual device.
Note: The shift direction shown in Figure 20-4 applies to both MSB-first and LSB-first
operation.
MCT05778
Shift Clock SCLK with:
Transmit Data
First
Bit
Shift Data
Latch Data
Last
Bit
SSC Pins
MTSR / MRST
CON.PO = 0
CON.PH = 0
CON.PO = 0
CON.PH = 1
CON.PO = 1
CON.PH = 0
CON.PO = 1
CON.PH = 1
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