TC1796
System Units (Vol. 1 of 2)
On-Chip System Buses and Bus Bridges
User’s Manual 6-58 V2.0, 2007-07
Buses, V2.0
6.5.5.4 BCU Service Request Control Register
In case of a bus error, the BCU generates an interrupt request to the selected service
provider (usually the CPU). This interrupt request is controlled through a standard
service request control register.
Note: Further details on interrupt handling and processing are described in Chapter 14
of this TC1796 System Units (Vol. 1 of 2) User’s Manual.
SBCU_SRC
SBCU Service Request Control Register
(FC
H
) Reset Value: 0000 0000
H
RBCU_SRC
RBCU Service Request Control Register
(FC
H
) Reset Value: 0000 0000
H
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
r
1514131211109876543210
SET
R
CLR
R
SRR SRE TOS 0 SRPN
w w rh rw r r rw
Field Bits Type Description
SRPN [7:0] rw Service Request Priority Number
TOS [11:10] r Type of Service Control
The SBCU/RBCU can only be serviced by the CPU.
SRE 12 rw Service Request Enable
SRR 13 rh Service Request Flag
CLRR 14 w Request Clear Bit
SETR 15 w Request Set Bit
0 [9:8],
[31:16]
r Reserved
Read as 0; should be written with 0.
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