Infineon Technologies TC1796 - 13.9.3 Burst Mode Access Phases; 13.9.4 Programmable Parameters

TC1796
System Units (Vol. 1 of 2)
LMB External Bus Unit
User’s Manual 13-68 V2.0, 2007-07
EBU, V2.0
Note: The EBU will issue an LMB Error Acknowledge if an attempt is made to write to an
address that is programmed as Burst Flash unless a lower priority write-enabled
region exists at the same address.
13.9.3 Burst Mode Access Phases
Accesses to asynchronous devices are composed of a number of standard Access
Phases (which are detailed in Section 13.7). The standard access phases for Burst
Flash devices are:
• AP: Address Phase (compulsory - see Page 13-41)
• CD: Command Delay Phase (optional - see Page 13-43)
• CP: Command Phase (compulsory - see Page 13-43)
• BP: Burst Phase (compulsory - see Page 13-46)
• RP: Recovery Phase (optional - see Page 13-47)
Note: During a burst access, the Burst Phase (BP) is repeated the required number of
times to complete the burst length.
13.9.4 Programmable Parameters
Table 13-19 lists the programmable parameters for Burst Flash accesses. These
parameters only apply only when the AGEN bit field in the EBU_BUSCONx or
EBU_EMUBC register for a particular memory region is set to 010
B
or 101
B
(Burst Flash
access).