TC1796
Peripheral Units (Vol. 2 of 2)
Analog-to-Digital Converter (ADC)
User’s Manual 25-36 V2.0, 2007-07
ADC, V2.0
25.1.4.4 Power-Up Calibration Time
When the A/D Converter becomes clocked after a reset operation, a power-up
calibration is automatically performed in order to correct gain and offset errors of the A/D
Converter. A running power-up calibration is indicated by status flag STAT.CAL. To
achieve best calibration results, the reference voltages as well as the supply voltages
must be stable during the power-up calibration. The first A/D conversion can be started
after the power-up calibration is finished (STAT.CAL = 0).
The power-up calibration takes 3840 clock cycles of the A/D Converter clock f
ANA
. After
a reset operation, the A/D Converter is disabled and becomes enabled when registers
ADC0_CLC and ADC0_FDR are written with appropriate values. Power-up calibration
starts when the analog part of the A/D Converter is clocked after a reset operation.
The following example shows the setup for the fastest achievable (best case) power-up
calibration time at f
SYS
= 75 MHz. Note that the maximum frequency of f
ANA
must not
exceed 10 MHz. See also Page 25-103 for further details on the ADC module clock
generation.
Example (f
ADC
= 75 MHz):
• f
SYS
= f
CLC
= 75 MHz
• f
ADC
= f
CLC
/ 1.875 = 40 MHz (Setting FDR for divider ratio 1.875)
• f
BC
= f
ADC
/ 1 = 40 MHz (CON.CTC = 00
H
)
• f
ANA
= f
BC
/ 4 = 10 MHz (fixed divider, f
ANA
max. frequency)
• t
ANA
= 1 / f
ANA
= 0.1 µs
These values result in a best case power-up calibration time of 3840 × t
ANA
= 384 µs.
The best case power-up calibration time as discussed above is of course increased by
decreasing the f
ANA
clock frequency. Note that the changing of clock related parameters
is not recommended during a running power-up calibration.
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