TC1796
Peripheral Units (Vol. 2 of 2)
Micro Second Channel (MSC)
User’s Manual 21-62 V2.0, 2007-07
MSC, V2.0
21.3 MSC Module Implementation
This section describes the MSC module interfaces as they are implemented in the
TC1796. It especially covers clock control, port and on-chip connections, interrupt
control, and address decoding.
21.3.1 Interface Connections of the MSC Modules
Figure 21-29 shows the TC1796-specific implementation details and interconnections of
the MSC0 and MSC1 modules.
Each MSC module is supplied by a separate clock control, address decoding, and
interrupt control logic. Two of the four modules’ service request outputs are connected
to interrupt nodes, and two with the DMA controller. Outputs of the GPTA0, GPTA1, and
LTCA2 modules are connected to the alternate input buses ALTINL/ALTINH. The
emergency stop output from the SCU controls the corresponding inputs of both MSC
modules.
The serial data and clock outputs of the downstream channels of each MSC module are
connected to dedicated LVDS differential output drivers. After a reset operation, all
LVDS outputs are disabled and in power-down mode. They must be enabled before
usage by setting SCU_CON.LDEN = 1.
Additionally, the positive serial clock (FCLP) and the positive data output (SOP) are
available at GPIO lines of Port 5 and Port 9. The device select outputs (ENxy) are wired
to GPIO lines of Port 5 and Port 9. Two Port 5 input lines are connected to the upstream
channel serial data inputs.
Each of the MSC module’s downstream channel serial data inputs is connected to one
port line of Port 5.
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