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Infineon Technologies TC1796 User Manual

Infineon Technologies TC1796
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TC1796
System Units (Vol. 1 of 2)
On-Chip System Buses and Bus Bridges
User’s Manual 6-21 V2.0, 2007-07
Buses, V2.0
The Bus Switch in the DMA controller operates as a bus bridge between the SPB and
RPB.
6.4.2 Bus Transaction Types
This section describes the SPB transaction types.
Single Transfers
Single transfers are byte, half-word, and word transactions that target any slave
connected either to SPB or RPB. Note that the LFI Bridge operates as an SPB master.
Block Transfers
Block transfers operate in principle in the same way as single transfers do, but one
address phase is followed by multiple data phases. Block transfers can be composed of
2 word, 4 word, or 8 word transfers.
Note: In general, block transfers (2 word, 4 word, or 8 word) cannot be executed in the
TC1796 with peripheral units that operate as FPI Bus slaves during an FPI Bus
transaction.
Block transfers are initiated by the following CPU instructions: LD.D, LD.DA, MOV.D,
ST.D and ST.DA. The BCOPY instruction of the PCP also initiates a block transfer
transaction on the FPI Bus.
Atomic Transfers
Atomic transfers are generated by LDMST, ST.T and SWAP.W instructions that require
two single transfers. The read and write transfer of an atomic transfer are always locked
and cannot be interrupted by another bus masters. Atomic transfers are also referenced
as read-modify-write transfers.
Note: See also Table 6-12 for available FPI Bus transfer types.
6.4.3 Reaction of a Busy Slave
If an FPI Bus slave is busy at an incoming FPI Bus transaction request, it can delay the
execution of the FPI Bus transaction. The requesting FPI Bus master releases the
FPI Bus for one cycle after the FPI Bus transaction request, in order to allow the FPI
slave to indicate if it is ready to handle the requested FPI Bus transaction. This sequence
is repeated as long as the slave indicates that it is busy.
Note: For the FPI Bus default master, the one cycle gap does not result in a performance
loss because it is granted the FPI Bus in this cycle as default master if no other
master requests the FPI Bus for some other reasons.

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Infineon Technologies TC1796 Specifications

General IconGeneral
BrandInfineon Technologies
ModelTC1796
CategoryController
LanguageEnglish