TC1796
System Units (Vol. 1 of 2)
System Control Unit
User’s Manual 5-35 V2.0, 2007-07
SCU, V2.0
5.4 Special System Interrupts
For some of the possible interrupts in the system, the interrupt control logic is not directly
controlled in the module, but via the SCU, e.g. for the FPU interrupts, which are
generated in the CPU, but have to be processed outside the CPU.
5.4.1 FPU Interrupts
The FPU provides two interrupts outputs that are activated in case of error conditions:
• Signal FPU_Exception1, which is activated if any of the error flags including the
inexact flag FX is set
• Signal FPU_Exception2, which is activated if any of the error flags excluding the
inexact flag FX is set
Both interrupts are combined to one interrupt request output that is controlled by register
DMA_SYSSCR0 in the DMA controller. Bit SCU_CON.FIEN determines whether an
inexact condition will lead to an interrupt or not.
When an FPU interrupt is generated, the related FPU status flags are latched into the
corresponding bits of the SCU Status Register SCU_STAT (see Page 5-67). Thus, the
status of the last floating point instruction that caused an interrupt can be read from
SCU_STAT.
The exception status information at the FPU output bus FPU_Exception_PSW is
connected to the bits in the SCU_STAT register as shown in Figure 5-6.
Figure 5-6 FPU Interrupt Control
MCA05618
SCU_STAT
FXIFUIFZIFVIFII
FPU_Exception_PSW
43210
30 29 28 27 26
FPU
SCU_CON
FIEN
0
&
FPU_Exception2
FPU_Exception1
To interrupt
node
in the DMA
Controller
Latch
To PSW
≥1
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