TC1796
System Units (Vol. 1 of 2)
CPU Subsystem
User’s Manual 2-8 V2.0, 2007-07
CPU, V2.0
2.3.5 Interrupt System
An interrupt request can be generated by the TC1796 on-chip peripheral units, or it can
be generated by external events. Requests can be targeted to either the CPU, or to the
Peripheral Control Processor (PCP).
The TC1796 interrupt system evaluates service requests for priority and to identify
whether the CPU or PCP should receive the request. The highest-priority service request
is then presented to the CPU (or PCP) by way of an interrupt.
The term “interrupt” is used generally to mean an event directed to the CPU, while the
term “service request” describes an event that can be directed to either the CPU or the
PCP. For more information, refer to Chapter 11 of this TC1796 User’s Manual.
2.3.6 Trap System
The following traps have implementation-specific properties. For a complete description
of the trap system, refer to the TriCore 1 Architecture Manual - Trap System.
UOPC - Unimplemented Opcode (TIN 2)
The TC1796 UOPC trap is raised on optional MMU instructions, coprocessor two and
coprocessor three instructions.
OPD - Invalid Operand (TIN 3)
The TC1796 CPU does not raise OPD traps.
DSE - Data Access Synchronous Error (TIN 2)
The Data Access Synchronous Bus Error (DSE) trap is generated by the DMI on a DMI
control register access error, LMB Bus access error, or a DMI scratch memory range
error. The exact cause of the error can be read in the DMI Synchronous Trap Flag
Register, DMI_STR. DSE traps occur on load accesses.
DAE - Data Access Asynchronous Error (TIN 3)
The Data Access Asynchronous Error Trap (DAE) is generated by the DMI on either a
DMI control register access error, LMB Bus access error, or a DMI scratch memory
range error. The exact cause of the error can be read via the DMI Asynchronous Trap
Flag Register, DMI_ATR. DAE traps occur on store accesses.
To Next Page
Loading...
Need help?
General