TC1796
System Units (Vol. 1 of 2)
Reset and Boot Operation
User’s Manual 4-10 V2.0, 2007-07
Reset, V2.0
reset sequence, the TC1796 will again attempt to execute the initialization code. If still
the code cannot be executed because of connection problems, the WDTOE bit will not
have been cleared by software. Again, the Watchdog Timer will time out and generate a
Watchdog Timer reset. However, this time the reset circuitry detects that WDTOE is still
set while a Watchdog Timer error has occurred, indicating danger of cyclic resets. The
reset circuitry then puts the TC1796 in Reset Lock. This state can only be deactivated
again through a power-on reset.
4.2.5 Debug System Reset
The debug system is not automatically reset by the regular resets except for the power-
on reset. It is not effected by a software resets and by a Watchdog Timer reset. A
hardware reset becomes only effective if at the same time the OCDS reset is active as
well.
Note: TriCore, PCP, DMA, RBCU and SBCU have integrated debug modules that are
part of the debug system.
4.2.6 Module Reset Behavior
Table 4-2 lists how the various functions of the TC1796 are affected through a reset
depending on the reset type. A black square means that this function/unit is reset to its
default state.
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