Infineon Technologies TC1796 - 23.5.6.2 Programmable Address Sub-Range Definitions

TC1796
Peripheral Units (Vol. 2 of 2)
Micro Link Interface (MLI)
User’s Manual 23-143 V2.0, 2007-07
MLI, V2.0
23.5.6.2 Programmable Address Sub-Range Definitions
In the TC1796, two of four possible programmable address range extensions are
implemented for internal memory areas:
• 8-Kbyte Dual-Ported RAM (DPRAM) assigned to address range 18;
sub-ranges are controlled by bit fields ARR.SIZE0 and ARR.SLICE0
(see Table 23-16).
• 64-Kbyte SRAM assigned as address range 29;
sub-ranges are controlled by bit fields ARR.SIZE1 and ARR.SLICE1
(see Table 23-17).
Attention: Bit fields ARR.SLICE2/ARR.SIZE2 and ARR.SLICE3/ARR.SIZE3 are not
used in TC1796.
The coding of bit fields SIZE0 and SLICE0 for the DPRAM sub-range access protection
are defined as shown in Table 23-16.
Table 23-16 DPRAM Address Protection Sub-Range Definitions
SIZE0 Sub-Ranges SLICE0 Selected Address Range
000
B
32 sub-ranges of
64 bytes
00000
B
00001
B
…
11111
B
F010 A000
H
to F010 A03F
H
F010 A040
H
to F010 A07F
H
…
F010 A7C0
H
to F010 A7FF
H
F010 A800
H
to F010 BFFF
H
is not selectable
001
B
32 sub-ranges of
128 bytes
00000
B
00001
B
…
11111
B
F010 A000
H
to F010 A07F
H
F010 A080
H
to F010 A0FF
H
…
F010 AF80
H
to F010 AFFF
H
F010 B000
H
to F010 BFFF
H
is not selectable
010
B
32 sub-ranges of
256 bytes
00000
B
00001
B
…
11111
B
F010 A000
H
to F010 A0FF
H
F010 A100
H
to F010 A1FF
H
…
F010 BF00
H
to F010 BFFF
H
011
B
16 sub-ranges of
512 bytes
X0000
B
X0001
B
…
X1111
B
F010 A000
H
to F010 A1FF
H
F010 A200
H
to F010 A3FF
H
…
F010 BE00
H
to F010 BFFF
H
100
B
8 sub-ranges of
1Kbyte
XX000
B
XX001
B
…
XX111
B
F010 A000
H
to F010 A3FF
H
F010 A400
H
to F010 A7FF
H
…
F010 BC00
H
to F010 BFFF
H