TC1796
Peripheral Units (Vol. 2 of 2)
Fast Analog-to-Digital Converter (FADC)
User’s Manual 26-9 V2.0, 2007-07
FADC, V2.0
26.1.3 Channel Triggers
As shown in Figure 26-4, the trigger behavior of an FADC channel x is determined by
its channel x trigger control logic. An FADC channel x can be triggered by three trigger
sources:
• External trigger source input signals TS[7:0]
• Internal channel x timer trigger signal
• Internal neighbor channel trigger signal
If one of these trigger sources is selected, becomes active, and the gating logic
(controlling the external gating source inputs GS[7:0]) is programmed to enable trigger
signals (signal ECHTIMx set), the conversion request flag CRFx becomes set indicating
a valid request for FADC channel x.
The gating source input and gating mode selection logic generate an enable signal for
channel x timer that determines whether any of the three conversion trigger signal
sources is allowed to set the channel x conversion request flag CRFx.
This control logic does the following control tasks:
• Gating source input selection (CFGRx.GSEL)
• Gating mode selection (CFGRx.GM)
• Trigger source input selection (CFGRx.TSEL)
• Trigger mode selection (CFGRx.TM)
• Channel timer request generation
• Conversion request flag set/clear control
All these control tasks are executed independently in each of the four FADC channels.
Figure 26-4 Channel Trigger Control Logic
MCA06041_mod
GSEL
CFGRx
Gating
Mode
Selection
GM
CFGRx
&
TSEL
CFGRx
Edge
Detection
Unit
TM
CFGRx
Channel x
Conversion
Trigger
Channel x
Timer
Enable
Trigger
GS[7:0]
TS[7:0]
Set
CRFx
CRSR
Channel x Trigger
Control
To other
FADC
Channels
Neighbor Channel
Trigger NCTx
RCRFx
FMR
SCRFx
Set
Clear
Conversion
Started
Clear
ECHTIMx
3 2
3 2
≥1
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